Thin film capacitor and electronic circuit substrate having the same

ABSTRACT

To provide a thin film capacitor having high adhesion performance with respect to a multilayer substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. A height of the first electrode layer is lower than a height of the second electrode layer. This enhances adhesion performance when the thin film capacitor is embedded in a multilayer substrate and improves ESR characteristics.

TECHNICAL FIELD

The present invention relates to a thin film capacitor and an electronic circuit substrate having the same, and more particularly to a thin film capacitor using a metal foil and an electronic circuit substrate having the same.

BACKGROUND ART

A decoupling capacitor is generally mounted on an IC-mounted circuit board so as to stabilize the potential of a power supply to be fed to the IC. A laminated ceramic chip capacitor is typically used as the decoupling capacitor, and a required decoupling capacitance is ensured by mounting many laminated ceramic chip capacitors on the surface of a circuit board.

However, in recent years, a space for mounting many laminated ceramic chip capacitors is sometimes insufficient due to miniaturization of circuit boards. Thus, a thin film capacitor capable of being embedded in a circuit board is sometimes used in place of the laminated ceramic chip capacitor (see Patent Documents 1 to 4).

In the thin film capacitor described in Patent Document 1, a porous metal substrate is used, and an upper electrode is formed on the surface of the porous metal substrate through a dielectric film. In the thin film capacitor described in Patent Document 2, a metal substrate in which one main surface thereof is roughened is used, and an upper electrode is formed on the roughened surface of the metal substrate through a dielectric film. In the thin film capacitors described in Patent Documents 3 and 4, a conductive porous substrate is formed as a support part, and an upper electrode is formed on a roughened surface of the conductive porous substrate through a dielectric film.

CITATION LIST Patent Document

[Patent Document 1] International Publication WO 20 2015/118901

[Patent Document 2] International Publication WO 2018/092722

[Patent Document 3] International Publication WO 2017/026247

[Patent Document 4] International Publication WO 2017/014020

SUMMARY OF THE INVENTION Problem to be Solved by the Invention

However, the thin film capacitor described in Patent Document 1 has a side surface electrode structure, so that the line length of the electrode is long, which causes a structural problem of increasing an ESR (Equivalent Series Resistance and an ESL (Equivalent Series Inductance). In addition, the thin film capacitor described in Patent Document 1 uses a metal substrate which is made entirely porous, so that it is not easy to separate the lower electrode constituted by the metal substrate and the upper electrode covering the metal substrate through a dielectric film, which disadvantageously makes it likely to cause a short circuit failure. In the thin film capacitor described in Patent Document 2, one main surface of the metal substrate functions as an upper electrode, and the other surface thereof functions as a lower electrode, so that it is necessary to route the electrode through the side surface of the element in order to dispose a pair of terminal electrodes on the same plane, complicating the structure. In the thin film capacitors described in Patent Documents 3 and 4, a pair of terminal electrodes are disposed on both surfaces of a metal substrate, respectively, preventing access to the terminal electrode pair from one side. In addition, the presence of the support increases the entire thickness.

It is therefore an object of the present invention to provide an improved thin film capacitor and an electronic circuit substrate having the same.

Means for Solving the Problem

A thin film capacitor according to the present invention include: a metal foil having one roughened main surface, a dielectric film covering the one main surface of the metal foil and having an opening through which the metal foil is partly exposed, a first electrode layer contacting the metal foil through the opening, and a second electrode layer contacting the dielectric film without contacting the metal foil, wherein the first electrode layer is lower in height than the second electrode layer.

A manufacturing method for a thin film capacitor according to the present invention includes roughening one main surface of a metal foil, forming a dielectric film on the roughened one main surface of the metal foil, removing a part of the dielectric film to expose a part of the metal foil; and forming a first electrode layer that contacts the part of the metal foil and a second electrode layer that contacts the dielectric film without contacting the part of the metal foil, wherein the first electrode layer is lower in height than the second electrode layer.

Advantageous Effects of the Invention

According to the present invention, an opening is formed in a part of the dielectric film, so that it is possible to dispose a pair of terminal electrodes on the same plane without using a side surface electrode or the like. In addition, since the first electrode layer is lower in height than the second electrode layer, an adhesion performance is enhanced when embedded in a multilayer substrate and an ESR characteristics is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to an embodiment of the present invention.

FIG. 1B is a schematic plan view of the thin film capacitor 1.

FIG. 1C is a schematic cross-sectional view illustrating an example in which a conductive member 32 is omitted from the thin film capacitor 1.

FIG. 1D is a schematic plan view of the thin film capacitor 1 illustrated in FIG. 1C.

FIG. 2 is a schematic cross-sectional view for explaining the shape of a side surface 13 of the thin film capacitor 1.

FIG. 3 is a process view for explaining a manufacturing method for the thin film capacitor 1.

FIG. 4 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 5A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 5B is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 6 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 7A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 7B is a schematic plan view of FIG. 7A.

FIG. 8A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 8B is a schematic plan view of FIG. 8A.

FIG. 9 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 10 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 11A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 11B is a schematic plan view of FIG. 11A.

FIG. 12A is a schematic cross-sectional view illustrating an example of the formation position of an insulating member 21.

FIG. 12B is a schematic cross-sectional view illustrating another example of the formation position of an insulating member 21.

FIG. 13 is a schematic cross-sectional view illustrating an example of the shape of the insulating member 21.

FIG. 14A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 14B is a schematic plan view of FIG. 14A.

FIG. 15A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 15B is a schematic plan view of FIG. 15A.

FIG. 16A is a schematic cross-sectional view illustrating a case where the crystal particle diameter of a metal foil 10 is large.

FIG. 16B is a schematic plan view of FIG. 16A.

FIG. 17A is a schematic cross-sectional view illustrating a case where the crystal particle diameter of a metal foil 10 is small.

FIG. 17B is a schematic plan view of FIG. 17A.

FIG. 18 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 19 is a schematic plan view of FIG. 18 .

FIG. 20A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 20B is a schematic plan view of FIG. 20A.

FIG. 21 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 22A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 22B is a schematic plan view of FIG. 22A.

FIG. 23A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 23B is a schematic plan view of FIG. 23A.

FIG. 24A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 24B is a schematic plan view of FIG. 24A.

FIG. 25A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 25B is a schematic plan view of FIG. 25A.

FIG. 26A is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 26B is a schematic plan view of FIG. 26A.

FIG. 27 is a process view for explaining the manufacturing method for the thin film capacitor 1.

FIG. 28 is a schematic cross-sectional view illustrating an electronic circuit substrate having a configuration in which the thin film capacitor 1 is embedded in a multilayer substrate 100.

FIG. 29 is a schematic cross-sectional view illustrating an electronic circuit substrate having a configuration in which the thin film capacitor 1 is mounted on the surface of a multilayer substrate 300.

FIG. 30 is a table indicating an evaluation results of samples.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to an embodiment of the present invention. FIG. 1B is a schematic plan view of the thin film capacitor 1.

As illustrated in FIGS. 1A and 1B, the thin film capacitor 1 includes a metal foil 10, ring-shaped or polygonal annular insulating members 21 and 22 formed on an upper surface 11 of the metal foil 10, conductive members 31 and 32 formed on the upper surface 11 of the metal foil 10 and partitioned by the insulating members 21 and 22, a terminal electrode 51 connected to the conductive member 31 through a seed layer 40, and a terminal electrode 52 connected to the conductive member 32 through the seed layer 40. The metal foil 10 is made of a metal material such as aluminum, copper, chrome, nickel, or tantalum, and upper and lower surfaces 11 and 12 thereof positioned on the mutually opposite sides are each at least partly roughened. Aluminum is most preferable as the material of the metal foil 10. A dielectric film D is formed on the upper and lower surfaces 11 and 12 of the metal foil 10. The insulating members 21 and 22 are each made of, for example, resin. The conductive members 31 and 32 are each made of, for example, a conductive polymer material. The seed layer 40 and terminal electrodes 51 and 52 are each made of, for example, copper, nickel, or gold, an alloy thereof, or a layer structure thereof.

The height of the upper surface of the terminal electrode 51 is H1, and the height of the upper surface of the terminal electrode 52 is H2. The height H2 of the upper surface of the terminal electrode 52 is lower than the height H1 of the upper surface of the terminal electrode 51. The difference between the height H1 and the height H2 is H1−H2. As described above, in the thin film capacitor 1 according to the present embodiment, the height H2 of the upper surface of the terminal electrode 52 is lower than the height H1 of the upper surface of the terminal electrode 51, so that adhesion performance when the thin film capacitor 1 is embedded in a multilayer substrate can be enhanced. That is, when the height H2 of the upper surface of the terminal electrode 52 is equal to the height H1 of the upper surface of the terminal electrode 51, the interface between a wiring pattern in the multilayer substrate and the terminal electrodes 51 and 52 becomes more likely to be peeled off because of stress in the in-plane direction; while when the height H2 of the upper surface of the terminal electrode 52 is lower than the height H1 of the upper surface of the terminal electrode 51, the in-plane stress is distributed. As a result, connection strength between the wiring pattern in the multilayer substrate and the terminal electrodes 51 and 52 increases to enhance reliability.

The ring-shaped or polygonal annular insulating member 21 is provided in a slit that electrically isolating an electrode layer including the terminal electrode 51 and conductive member 31 from an electrode layer including the terminal electrode 52 and conductive member 32. The terminal electrode 52 and conductive member 32 are positioned within an area surrounded by the insulating member 21, and the terminal electrode 51 and conductive member 31 are positioned outside the area surrounded by the insulating member 21 and within an area surrounded by the insulating member 22. In the area surrounded by the insulating member 21, a part of or the entire dielectric film D formed on the upper surface 11 of the metal foil 10 is removed, and thus an opening is formed in the dielectric film D. As a result, the terminal electrode 52 is electrically connected to the metal foil 10 through the conductive member 32. Alternatively, as illustrated in FIGS. 1C and 1D, the conductive member 32 may be omitted to connect the metal foil 10 and terminal electrode 52 directly or through the seed layer 40. In this case, it is easier to make the height H2 of the upper surface of the terminal electrode 52 lower than the height H1 of the upper surface of the terminal electrode 51. Moreover, since the terminal electrode 52 directly contacts with the metal foil 10, the ESR is also reduced.

On the other hand, at the outside of the area surrounded by the insulating member 21, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed. That is, the conductive member 31 contacts the dielectric film D without contacting the metal foil 10, so that the terminal electrode 51 and metal foil 10 are electrically isolated from each other. Thus, the terminal electrodes 51 and 52 function as a pair of capacitance electrodes opposite to each other through the dielectric film D. The dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, that is, the surface area of the upper surface 11 is increased, allowing a large capacitance to be obtained.

At the outside of the area surrounded by the insulating member 22, the dielectric film D formed on the upper surface 11 of the metal foil 10 is exposed. The roughened surface is thus exposed at the outer peripheral portion of the thin film capacitor 1, so that adhesion when the thin film capacitor 1 is embedded in a multilayer substrate can be enhanced. A side surface 13 of the metal foil 10 is not roughened and is covered with an insulating film 14. The ring-shaped or polygonal annular insulating member 22 exists between the conductive member 31 and the side surface 13 of the metal foil 10, and a clearance area where no conductive member exists is provided at the outside of the ring-shaped or polygonal annular insulating member 22, so that even when the insulating film 14 is thin, a short circuit between the conductive member 31 and metal foil 10 is prevented.

The crystal particle diameter of the center portion (non-roughened portion) of the metal foil 10 is preferably less than 15 μm in the planar direction (direction parallel to the upper and lower surfaces 11 and 12) and less than 5 μm in the thickness direction (direction orthogonal to the upper and lower surfaces 11 and 12), and crystal orientations are preferably aligned with the planar direction as much as possible. This can enhance the positional accuracy of the side surface 13 as will be described later.

The thin film capacitor 1 can be used as a decoupling capacitor when being embedded in a multilayer substrate. The thickness of the thin film capacitor 1 is as very thin as, for example, 50 μm or less. Thus, when the terminal electrode 51 and conductive member 31 are formed on the upper surface 11 side, the thin film capacitor 1 is more likely to protrude toward the lower surface 12 side. Therefore, in order to suppress warpage of the element when it is embedded in the multilayer substrate, the following configuration is preferable. That is, when a straight line L1 extending along the upper surface 11, a straight line L2 extending along the lower surface 12, and a straight line L3 extending along the side surface 13 are defined in the cross section illustrated in FIG. 2 , an angle θa formed by the straight lines L2 and L3 is preferably more than 20° and less than 80° (20°<θa<80°). This means that the lower surface 12 preferably has a larger area than the upper surface 11. This improves adhesion between the side surface 13 of the thin film capacitor 1 and the multilayer substrate, thus making it possible to increase strength and reliability of the thin film capacitor 1. In this case, 30°≤θa≤60° is more preferably satisfied. When the angle θa is designed to fall within the above range, warpage of the thin film capacitor 1 at the time of mounting is reduced, and a contact area between the side surface 13 and the insulating resin constituting the multilayer substrate is controlled optimally, so that strength and reliability of the thin film capacitor 1 can be further improved. The side surface 13 may be curved such that the angle θa becomes larger toward the upper surface 11 and becomes smaller toward the lower surface 12. When the angle θa is not constant as just described, the value of the angle θa is defined by an average value.

The following describes an example of a manufacturing method for the thin film capacitor 1.

First, the metal foil 10 made of aluminum with a thickness of about 50 μm is prepared (FIG. 3 ), and the upper and lower surfaces 11 and 12 are each etched for roughening (FIG. 4 ). In place of roughening the flat metal foil 10, the metal foil 10 may be formed by sintering metal powder. As a result, there are formed, in the metal foil 10, a porous layer 11 a positioned on the upper surface 11 side and a porous layer 12 a positioned on the lower surface 12 side. A non-porous layer 10 a, which is not subjected to roughening, is positioned between the porous layers 11 a and 12 a. At this time, it is sufficient to apply roughening to at least the upper surface 11, and the lower surface 12 may not necessarily be roughened; however, roughening both the upper and lower surfaces 11 and 12 can prevent warpage of the metal foil 10. The upper surface 11 is preferably etched under a condition that the surface area thereof is increased as much as possible. When both the upper and lower surfaces 11 and 12 are roughened, they may be etched under different etching conditions. For example, the lower surface 12 may be roughened under a condition that adhesion with respect to the multilayer substrate is enhanced as much as possible.

Then, the dielectric film D is formed on the surface of the metal foil 10 (FIG. 5A). The dielectric film D may be formed through oxidation of the metal foil 10 or using a film forming method excellent in coverage performance, such as an ALD method, a CVD method, or a mist CVD method. Examples of the material of the dielectric film D include Al₂O₃, TiO₂, Ta₂O₅, SiNx, TiNx, and TaNx. Amorphous may be used as the material of the dielectric film D. In this case, the composition ratio of the dielectric film D is not always the same as the composition ratio described above. At this time, it is sufficient to form the dielectric film D on at least the upper surface 11, and the dielectric film D may not necessarily be formed on the lower surface 12; however, forming the dielectric film D also on the lower surface 12 can provide an insulating property to the lower surface 12. As illustrated in FIG. 5B, the dielectric film D formed on the lower surface 12 may have the same composition ratio as the dielectric film D formed on the upper surface 11, may be a barrier film E having a different composition ratio, and may be a laminated structure of the dielectric film D and barrier film E. When the barrier film E exists on the lower surface 12 of the metal foil 10, it is possible to suppress intrusion of reaction product gas generated from resin constituting the multilayer substrate at the time of curing the multilayer substrate. After formation of the dielectric film D or barrier film E, a base material 60 for conveyance is stuck to the lower surface 12 of the metal foil 10 (FIG. 6 ).

Then, a photosensitive resist is formed on the upper surface 11 of the metal foil 10, followed by exposure and development, to form a patterned resist 61 (FIGS. 7A and 7B). The resist 61 has an opening 62 for exposing the dielectric film D therethrough. The resist may be a positive type or a negative type.

Then, a part of or the entire dielectric film D is removed with the resist 61 used as a mask to expose the metal foil 10 through the opening 62 (FIGS. 8A and 8B). The dielectric film D can be removed using a reverse sputtering method, an ion milling method, a RIE method, a wet etching method, or the like. At this stage, the upper surface 11 of the metal foil 10 has already been roughened, so that by using the reverse sputtering method, ion milling method, RIE method or the like, it is possible to prevent spread of an etchant due to a capillary phenomenon. However, a liquid etchant may be used in this process. Although the surface of the exposed metal foil 10 and the dielectric film D constitute substantially the same plane in the example illustrated in FIG. 8A, the roughened metal foil 10 can protrude from the dielectric film D in some etching condition as illustrated in FIG. 9 .

Then, after removal of the resist 61 (FIG. 10 ), the insulating members 21 and 22 are formed on the upper surface 11 of the metal foil 10 (FIGS. 11A and 11B). The insulating members 21 and 22 can be formed by a photolithography patterning method, a screen printing method, a gravure printing method, an inkjet method, or the like. As a result, the insulating members 21 and 22 each have a tapered cross section as illustrated in FIG. 11A. The insulating member 21 may overlap (FIG. 12A) or may not overlap (FIG. 12B) a portion at which the metal foil 10 is exposed. Further, the insulating members 21 and 22 each may not necessarily have a symmetric cross section and, as illustrated in FIG. 13 , an angle θc of the outer part of the ring constituted by the insulating member 21 with respect to a center line C in the thickness direction of the metal foil 10 may be made smaller than an angle θb of the inner part of the ring with respect to the center line C to make wider the taper surface at the ring outer part than the taper surface at the ring inner part. The insulating member 21 contacts the conductive member 32 or terminal electrode 52 at the inner side surface thereof and contacts the conductive member 31 or terminal electrode 51 at the outer side surface thereof. With the above structure, abnormal stress is not generated during a contraction process in the formation of the insulating members 21 and 22, making it possible to reduce the occurrence of cracks at the roughened portion to thereby improve manufacturing yield.

Then, a photosensitive resist is formed on the upper surface 11 of the metal foil 10, followed by exposure and development, to form a patterned resist 64 (FIGS. 14A and 14B). The resist 64 has an opening 65 for exposing therethrough an area outside the insulating member 22. The resist may be a positive type or a negative type.

Then, the metal foil 10 is removed with the resist 64 used as a mask to individualize the metal foil 10 (FIGS. 15A and 15B). The metal foil 10 can be removed by a wet etching method using an etchant such as acid. In this case, even when a liquid etchant is used, it does not spread beyond the insulating member 22.

To individualize the metal foil 10 more accurately, the crystal particle diameter of the center portion (non-roughened portion) of the metal foil 10 is preferably less than 15 μm in the planar direction and less than 5 μm in the thickness direction, as described above. When the crystal particle diameter of the metal foil 10 is 15 μm or more in the planar direction and 5 μm or more in the thickness direction, crystal particles protrude from the inner wall of the side surface 13 as illustrated in FIGS. 16A and 16B to increase a variation in the size of the individualized metal foil 10. On the other hand, when the crystal particle diameter of the metal foil 10 is less than 15 μm in the planar direction and less than 5 μm in the thickness direction, the crystal particles appearing at the side surface 13 are small in size as illustrated in FIGS. 17A and 17B, thereby reducing variation in the size of the individualized metal foil 10.

Then, after removal of the resist 64 (FIGS. 18 and 19 ), the conductive member 31 in a paste or liquid form made of a conductive polymer material is formed in an area surrounded by the insulating member 22 and outside an area surrounded by the insulating member 21 (FIGS. 20A and 20B). The conductive member 31 is in a paste or liquid form and is thus filled up to the bottom of the porous layer 11 a by capillary action. As a result, the conductive member 31 contacts the dielectric film D without contacting the metal foil 10. Note that the conductive member 31 may be formed in the area surrounded by the insulating member 21.

Then, the seed layer 40 is formed on the entire surface (FIG. 21 ). The seed layer 40 can be formed using a sputtering method or the like. As a result, the seed layer 40 contacts the metal foil 10 in the area surrounded by the insulating member 21 and contacts the conductive member 31 in the area surrounded by the insulating member 22 and outside the area surrounded by the insulating member 21. Subsequently, a photosensitive resist is formed on the upper surface 11 of the metal foil 10, followed by exposure and development, to form a patterned resist 67 (FIGS. 22A and 22B). The resist 67 has openings 68 and 69. The opening 68 is positioned in the area surrounded by the insulating member 22 and outside the area surrounded by the insulating member 21. The opening 69 is positioned in the area surrounded by the insulating member 21. As a result, the seed layer 40 is exposed through the opening 69 in the area surrounded by the insulating member 21 and exposed through the opening 68 in the area surrounded by the insulating member 22 and outside the area surrounded by the insulating member 21. The resist may be a positive type or a negative type.

In this state, electrolytic plating is performed to form the terminal electrodes 51 and 52 (FIGS. 23A and 23B). As a result, the height H2 of the top surface of the terminal electrode 52 is lower than the height H1 of the top surface of the terminal electrode 51. Then, after removing the resist 67 by ashing or the like (FIGS. 24A and 24B), the seed layer 40 is removed (FIGS. 25A and 25B). After that, the insulating film 14 is formed on the side surface 13 of the metal foil 10 (FIG. 26 ), and the base material 60 for conveyance is removed by peeling or etching (FIG. 27 ), whereby the thin film capacitor 1 illustrated in FIGS. 1A and 1B is completed. The insulating film 14 can be formed by oxidizing the side surface 13 of the metal foil 10 by an ashing process for removing the resist 67 or a heat treatment process. The terminal electrodes 51 and 52 may each be formed in plural numbers, and at least one pair of the terminal electrodes 51 and 52 will suffice.

The thin film capacitor 1 according to the present embodiment may be embedded in a multilayer substrate 100 as illustrated in FIG. 28 or may be mounted on the surface of a multilayer substrate 300 as illustrated in FIG. 29 .

An electric circuit substrate illustrated in FIG. 28 has a configuration in which a semiconductor IC 200 is mounted on the multilayer substrate 100. The multilayer substrate 100 includes a plurality of insulating layers including insulating layers 101 to 104 and a plurality of wiring patterns including wiring patterns 111 and 112. The number of insulating layers is not particularly limited. In the example illustrated in FIG. 28 , the thin film capacitor 1 is embedded between the insulating layers 102 and 103. There are provided on the surface of the multilayer substrate 100 a plurality of land patterns including land patterns 141 and 142. The semiconductor IC 200 has a plurality of pad electrodes including pad electrodes 201 and 202. For example, one of the pad electrodes 201 and 202 is a power supply terminal, and the other one thereof is a ground terminal. The pad electrode 201 and land pattern 141 are connected to each other through a solder 211, and the pad electrode 202 and the land pattern 142 are connected to each other through a solder 212. The land pattern 141 is connected to the terminal electrode 51 of the thin film capacitor 1 through a via conductor 121, the wiring pattern 111, and a via conductor 131. The land pattern 142 is connected to the terminal electrode 52 of the thin film capacitor 1 through a via conductor 122, the wiring pattern 112, and a via conductor 132. With this configuration, the thin film capacitor 1 functions as a decoupling capacitor for the semiconductor IC 200.

An electric circuit substrate illustrated in FIG. 29 has a configuration in which a semiconductor IC 400 is mounted on the multilayer substrate 300. The multilayer substrate 300 includes a plurality of insulating layers including insulating layers 301 and 302 and a plurality of wiring patterns including wiring patterns 311 and 312. The number of insulating layers is not particularly limited. In the example illustrated in FIG. 29 , the thin film capacitor 1 is surface-mounted on a surface 300 a of the multilayer substrate 300. There are provided on the surface 300 a of the multilayer substrate 300 a plurality of land patterns including land patterns 341 to 344. The semiconductor IC 400 has a plurality of pad electrodes including pad electrodes 401 and 402. For example, one of the pad electrodes 401 and 402 is a power supply terminal, and the other one thereof is a ground terminal. The pad electrode 401 and the land pattern 341 are connected to each other through a solder 411, and the pad electrode 402 and the land pattern 342 are connected to each other through a solder 412. The land pattern 341 is connected to the terminal electrode 51 of the thin film capacitor 1 through a via conductor 321, the wiring pattern 311, a via conductor 331, and a solder 413. The land pattern 342 is connected to the terminal electrode 52 of the thin film capacitor 1 through a via conductor 322, the wiring pattern 312, the land pattern 344, and a via conductor 332, and a solder 414. With this configuration, the thin film capacitor 1 functions as a decoupling capacitor for the semiconductor IC 400.

While the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment, and various modifications may be made within the scope of the present invention, and all such modifications are included in the present invention.

EXAMPLES

Samples of a plurality of thin film capacitors having the same configuration as that of the thin film capacitor 1 illustrated in FIG. 1 were prepared with the difference (H1−H2) between the height H1 of the terminal electrode 51 and the height H2 of the terminal electrode 52 varied from one sample to another. The planar size of each sample was set to 5 mm×5 mm. Then, for each sample of the thin film capacitor, adhesive stress and ESR of the terminal electrodes 51 and 52 were measured.

In measurement of the adhesive stress, the lower surface 12 of the metal foil 10 was fixed to a support with epoxy resin, followed by connection of a stud pin to each of the terminal electrodes 51 and 52 and covering of the entire surface of each of the terminal electrodes 51 and 52 with epoxy resin. As the stud pin, P/N 901106 (diameter ϕ of adhesion surface=2.7 mm) manufactured by QUAD Group was used. The stud pin was pulled off upward in the vertical direction at a tensile speed of 20 mm/min using a force gauge (RZ-50 (500N) manufactured by AIKOH), and peeling strength when the stud pin was peeled off from the terminal electrode 51 or 52 was recorded. The peeling strength when the cumulative peeling probability was 50% for 30 stud pins was defined as the adhesive stress of each sample. In measurement of the ESR, a probe was made to contact the terminal electrodes 51 and 52 of each sample, and the ESR was measured using an impedance analyzer. The results are shown in FIG. 30 .

As shown in FIG. 30 , samples A1 to A6 in which the height H2 of the terminal electrode 52 was lower than the height Hl of the terminal electrode 51 was higher in adhesion stress and smaller in ESR than sample B1 in which the height H1 of the terminal electrode 51 was equal to the height H2 of the terminal electrode 52. In particular, in samples A2 to A5 in which the height difference H1−H2 was 1.0 μm to 7.0 μm, the adhesion stress was even higher, and the ESR was even smaller. Further, in samples A4 in which the height difference H1−H2 was 4.2 μm, the adhesion stress was the highest of all the samples, and the ESR was the smallest.

REFERENCE SINGS LIST

1: Thin film capacitor

10: Metal foil

10 a: Non-porous layer

11: Upper surface of metal foil

11 a: Porous layer

12: Lower surface of metal foil

12 a: Porous layer

13: Side surface of metal foil

14: Insulating film

21, 22: Insulating member

31, 32: Conductive member

40: Seed layer

51, 52: Terminal electrode

60: Base material for conveyance

61, 64, 67: Resist

62, 65, 68, 69: Opening

100, 300: Multilayer substrate

101 to 104, 301, 302: Insulating layer

111, 112, 311, 312: Wiring pattern

121, 122, 131, 132, 321, 322, 331, 332: Via conductor

141, 142, 341 to 344: Land pattern

200, 400: Semiconductor IC

201, 202, 401, 402: Pad electrode

211, 212, 411 to 414: Solder

300 a: Surface of multilayer substrate

D: Dielectric film

E: Barrier film 

1. A thin film capacitor comprising: a metal foil having one roughened main surface; a dielectric film covering the one main surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil, wherein the first electrode layer is lower in height than the second electrode layer.
 2. The thin film capacitor as claimed in claim 1, wherein the first and second electrode layers are separated from each other by an annular slit, wherein the first electrode layer is provided in a first area surrounded by the slit, and wherein the second electrode layer is provided in a second area positioned outside the slit.
 3. The thin film capacitor as claimed in claim 2, further comprising a first insulating member provided inside the slit and positioned between the first and second electrode layers.
 4. The thin film capacitor as claimed in claim 3, further comprising a second insulating member provided on the one main surface of the metal foil and surrounding the second electrode layer.
 5. The thin film capacitor as claimed in claim 1, wherein the second electrode layer includes a first conductive member contacting the dielectric film and made of a conductive polymer material and a second conductive member contacting the first conductive member and made of a metal material.
 6. The thin film capacitor as claimed in claim 5, wherein the first electrode layer includes a third conductive member contacting the metal foil and made of a conductive polymer material and a fourth conductive member contacting the third conductive member and made of a metal material.
 7. The thin film capacitor as claimed in claim 5, wherein the first electrode layer includes a fourth conductive member contacting the metal foil and made of a metal material.
 8. The thin film capacitor as claimed in claim 1, wherein the first electrode layer is lower in height than the second electrode layer by 1 or more.
 9. The thin film capacitor as claimed in claim 8, wherein the first electrode layer is lower in height than the second electrode layer by 2 μm or more.
 10. The thin film capacitor as claimed in claim 1, wherein a difference in height between the first and second electrode layers is 7 μm or less.
 11. The thin film capacitor as claimed in claim 1, wherein other main surface of the metal foil is roughened.
 12. An electronic circuit substrate comprising: a substrate having a wiring pattern; a semiconductor IC provided in the substrate; and the thin film capacitor as claimed in claim 1 provided in the substrate, wherein the first and second electrode layers of the thin film capacitor are connected to the semiconductor IC through the wiring pattern. 